Electronic design automation

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Electronic design automation (EDA) is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. This is sometimes referred to as ECAD (electronic computer-aided design) or just CAD. (Printed circuit boards and wire wrap both contain specialized discussions of the EDA used for those.)

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Terminology

The term EDA is also used as an umbrella term for computer-aided engineering, computer-aided design and computer-aided manufacturing of electronics in the discipline of electrical engineering. This usage probably originates in the IEEE Design Automation Technical Committee.

This article describes EDA specifically for electronics, and concentrates on EDA used for designing integrated circuits. The segment of the industry that must use EDA are chip designers at semiconductor companies. Large chips are too complex to design by hand.

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Growth of EDA

EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology. (See Moore's Law.) Some users are foundry operators, who operate the semiconductor fabrication facilities, or "fabs", and design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs.

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History

Before EDA, integrated circuits were designed by hand, and manually laid out. Some advanced shops used geometric software to generate the tapes for the Gerber photoplotter, but even those copied digital recordings of mechanically-drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually.

The history of modern EDA begins more or less with the publication of "Introduction to VLSI Systems" by Carver Mead and Lynn Conway in 1980. This groundbreaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a hundredfold increase in the complexity of the chips that could be designed, with improved access to design verification tools that used logic simulation. Often the chips were not just easier to lay out, but more correct as well, because their designs could be simulated more thoroughly before construction.

The earliest EDA tools were produced academically, and were in the public domain. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of UNIX utilities used to design early VLSI systems.

Another crucial development was the formation of MOSIS, a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic idea was to use reliable, low-cost, relatively low-technology IC processes, and pack a large number of projects per wafer, with just a few copies of each projects' chips. Cooperating fabricators either donated the processed wafers, or sold them at cost, seeing the program as helpful to their own long-term growth.

In 1981, 3 visionary managers left Tektronix, to found not only a company, but a new industry. At the time, analysts categorized Mentor Graphics as a niche within the “computer aided design” market, primarily mechanical design drafting tools for conceptualizing bridges, buildings and automobiles. In reality, the company was pioneering a new industry, the automation of electronic design, hence the evolution of an embryonic industry to a major force with its own, unique moniker “Engineering Design Automation.”

In 1985, Verilog, a popular high-level design language, was first introduced as a hardware description language by Gateway. In 1987, the U.S. Department of Defense funded creation of VHDL as a specification language. Simulators quickly followed these introductions, permitting direct simulation of chip designs: executable specifications. In a few more years, back-ends were developed to perform logic synthesis.

In 1994, Zuken Inc. in Japan was merged with Racal-Redac Ltd., an UK based subsidiary of Racal Electronics plc to form Zuken-Redac. It became one of the largest market share holder in the PCB design software market. Zuken-Redac was later renamed as Zuken Inc. after another merger with Incases Engineering Gmbh in 2000.

Many of the EDA companies acquire small companies with software or other technology that can be adapted to their core business. Most of the market leaders are rather incestuous amalgamations of many smaller companies. This trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs (the "tool flow").

While early EDA focused on digital circuitry, many new tools incorporate analog design, and mixed systems. This is happening because there is now a trend to place entire electronic systems on a single chip.

Current digital flows are extremely modular (see Integrated circuit design, Design closure, and Design flow (EDA)). The front ends produce standardized design descriptions that compile into invocations of "cells,", without regard to the cell technology. Cells implement logic or other electronic functions using a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools. Analog EDA tools are much less modular, since many more functions are required, they interact more strongly, and the components are (in general) less ideal.

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Product areas

EDA is divided into many (sometimes overlapping) sub-areas. They mostly align with the path of manufacturing from design to mask generation. The following applies to chip/ASIC/FPGA construction but is very similar in character to the areas of printed circuit board design:

  • Design and Architecture: design the chip's schematics, output in Verilog, VHDL, SPICE and other formats.
  • Floorplanning: The preparation step of creating a basic die-map showing the expected locations for logic gates, power & ground planes, I/O pads, and hard macros. (This is analogous to a city-planner's activity in creating residential, commercial, and industrial zones within a city block.)
  • Logic synthesis: translation of a chip's abstract, logical RTL-description (often specified via a hardware description language, or "HDL", such as Verilog or VHDL) into a discrete netlist of logic-gate (boolean-logic) primitives.
  • Behavioral Synthesis, High Level Synthesis or Algorithmic Synthesis: This takes the level of abstraction higher and allows automation of the architecture exploration process. It involves the process of translating an abstract behavioral description of a design to synthesizeable RTL. The input specification is in languages like behavioral VHDL, algorithmic SystemC, C++ etc and the RTL description in VHDL/Verilog is produced as the result of synthesis.
  • IP cores: provide pre-programmed design elements.
  • EDA databases: databases specialized for EDA applications. Needed since historically general purpose DBs did not provide enough performance.
  • Simulation: simulate a circuit's operation so as to verify correctness and performance.
    • Transistor Simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
    • RTL Simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.
    • Behavioral Simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
    • Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
  • Clock Domain Crossing Verification (CDC check): Similar to linting, but these checks/tools specialise in detecting and reporting potential issues like data loss, meta-stability due to use of multiple clock domains in the design.
  • Formal verification, also model checking: Attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as deadlock) cannot occur.
  • Equivalence checking: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalency at the logical level.
  • Power analysis and optimization: optimizes the circuit to reduce the power required for operation, without affecting the functionality.
  • Place and route, PAR: (for digital devices) tool-automated placement of logic-gates and other technology-mapped components of the synthesized gate-netlist, then subsequent routing of the design, which adds wires to connect the components' signal and power terminals.
  • Static timing analysis: Analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
  • Transistor layout: (for analog/mixed-signal devices), sometimes called polygon pushing – a prepared-schematic is converted into a layout-map showing all layers of the device.
  • Design for Manufacturability: tools to help optimize a design to make it as easy and cheap as possible to manufacture.
  • Design closure: IC design has many constraints, and fixing one problem often makes another worse. Design closure is the process of converging to a design that satisfies all constraints simultaneously.
  • Analysis of substrate coupling.
  • Physical verification, PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.
    • Design rule checking, DRC – checks a number of rules regarding placement and connectivity required for manufacturing.
    • Layout versus schematic, LVS – checks if designed chip layout matches schematics from specification.
    • Layout extraction, RCX – extracts netlists from layout, including parasitic resistors (PRE), and often capacitors (RCX), and sometimes inductors, inherent in the chip layout.
  • Mask data preparation, MDP: generation of actual lithography photomask used to physically manufacture the chip.
  • Manufacturing Test
    • Automatic test pattern generation, ATPG – generates pattern-data to systematically exercise as many logic-gates, and other components, as possible.
    • Built In Self Test, BIST – installs self-contained test-controllers to automatically test a logic (or memory) structure in the design
    • Design For Test, DFT – adds logic-structures to a gate-netlist, to facilitate post-fabrication (die/wafer) defect testing.
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Largest companies

Company Location Market Value (12/2005) Logo
Cadence Design Systems San Jose, California $5.17 billion Image:CadenceDesignSystemsLogo.GIF
Synopsys Mountain View, California $2.95 billion Image:SynopsysLogo.GIF
Mentor Graphics Wilsonville, Oregon $729 million Image:MentorGraphicsLogo.GIF
Magma Design Automation Inc Santa Clara, California $302 million Image:MagmaDALogo.gif
Zuken Inc. Yokohama, Japan $300 million Image:Zuken small2.gif
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See also

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External links

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Open source EDA tools

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References

ja:EDA ru:EDA

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