PA-RISC family

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Image:HP PA-RISC 7300LC.jpg PA-RISC is a microprocessor architecture developed by Hewlett-Packard's Systems & VLSI Technology Operation. As the name implies, it is an implementation using a RISC (Reduced Instruction Set Computing) design, where the PA stands for Precision Architecture. The design is also referred to as HP/PA for Hewlett Packard Precision Architecture. PA is considered by some to stand for Palo Alto, the location of HP's headquarters.

In the late 1980s HP was building three series of computers, all based on CISC CPUs. One line was the series of Motorola 68000-based workstations they took over when they purchased Apollo Computer, another their own HP 9000 line of workstations based on a custom silicon on sapphire (SOS) chip design, and finally the HP 3000 series minicomputers, based on their own 16-bit CPU. HP was looking to use the PA-RISC to move all of their machines to a single RISC CPU family.

The early PA-RISC chips were 32-bit designs. They were first used in a new series of HP 3000 machines in the late 1980s -- the 930 and 950, commonly known at the time as Spectrum systems, the name given to them in the development labs. These machines ran MPE/iX. The HP 9000 machines were soon upgraded with the PA-RISC processor as well, running the HP-UX version of UNIX.

Other operating systems ported to the PA-RISC processor include Mach, Linux, OpenBSD, NetBSD, NEXTSTEP, and an unreleased Windows NT.

An interesting aspect of the PA-RISC line is that most of its generations have no Level 2 cache. Instead large Level 1 caches are used, formerly as separate chips connected by a bus, and now integrated on-chip. Only the PA-7100LC and PA-7300LC had L2 caches. Another innovation of the PA-RISC was the addition of multimedia instructions (SIMD) in the form of MAX which were first introduced on the PA-7100LC.

The design was upgraded in 1996 to the PA-RISC 2.0 architecture, which is fully 64-bit. The first product of this series was the PA-8000, which featured ten functional units and an aggressive pipelining system. Another change was the splitting of the instruction cache, with separate caches for instructions that take long or short time to complete. The PA-8200 was released in 1997 and was much like the PA-8000 with better branch prediction, lower TLB miss rates, and larger, faster caches.

The PA-8500 design added the cache to the main chip, with 1.5MB of Level 1 cache. Consequently, it was a great performer for its time. With its introduction the Runway bus was upgraded to a DDR implementation providing ~2 GB/s peak bandwidth to memory. Its branch history table was doubled in size to 2048 entries and its translation lookaside buffer was increased from 120 to 160 entries.

The 8600 is essentially a higher clocked 8500 with a quasi-LRU instruction cache eviction policy. The 8700 is clocked higher than the 8600, to which it is otherwise similar, and has 2.25 MB of L1 cache. It also gained a quasi-LRU data cache eviction policy and data prefetch capability. It is worth noting that the relatively high latencies of the integrated L1, a tradeoff due to its size, may limit performance. However, the size of HP's integrated caches remain impressive for their process sizes.

The PA-8800, codenamed Mako, features 2 independent microprocessors on a single die. Thus each "chip" forms a 2-way SMP set. Each processor on the 8800 has a 1.5 MB L1 cache, but HP is leaving behind its L1-only design custom by including 32 MB of L2 cache using separate chips. The Runway bus has been replaced by the 6.4 GB/s Itanium2 bus, allowing greater bandwidth and the use of otherwise very similar server designs for both PA-RISC and Itanium.

The PA-8900 is similar to the 8800, but features a faster 64 MB shared L2 and slight core improvements such as better error detection and correction on caches. It is not a die shrink of the 8800, as was earlier rumored. It is the last in the PA-RISC line.

The core design introduced with the PA-8000 has not changed significantly to date; each later generation has concentrated only on increasing clock speed and integrating incremental improvements like larger caches and, finally, 2 cores on one chip. Along with the MIPS architecture, the PA-RISC is nearing the end of its lifecycle as a commercial UNIX-machine CPU.

Model History

Model	AKA	Year	Frequency [MHz]	Memory Bus [MB/s]	Process [µm]	Transistors [millions]	Die size [mm²]	Power [W]	Dcache [k]	Icache [k]	L2 cache	ISA
PCX-S	PA-7000	1989	66	?	1.0	0.58	201.6	?	256	256	—	1.1a
PCX-T	PA-7100	1992	33–100	?	0.8	0.85	196	?	2048	1024	—	1.1b
PCX-T	PA-7150	1994	125	?	0.8	0.85	196	?	2048	1024	—	1.1b
PCX-T'	PA-7200	1994	120	960	0.55	1.26	210	30	1024	2048	—	1.1c
PCX-L	PA-7100LC	1994	60–100	?	0.75	0.9	201.6	7–11	—	1	2 MB	1.1d
PCX-L2	PA-7300LC	1996	132–180	?	0.5	9.2	260.1	?	64	64	0–8 MB	1.1e
PCX-U	PA-8000	1996	160–180	960	0.5	3.8/4.5?	338/347?	?	1024	1024	—	2.0
PCX-U+	PA-8200	1997	200–240	960	0.5	3.8/4.5?	338/347?	?	2048	2048	—	2.0
PCX-W	PA-8500	1998	300–440	1920	0.25	140	467	?	1024	512	—	2.0
PCX-W+	PA-8600	2000	480–552	1920	0.25	140	467	?	1024	512	—	2.0
PCX-W2	PA-8700(+)	2001	625–875	1920	0.18	186	304	?	1536	768	—	2.0
Mako	PA-8800	2003	900–1000	6400	0.13	300	361	?	768/core	768/core	32 MB	2.0
Shortfin	PA-8900	2005	1000–1100	6400	0.13	?	?	?	768/core	768/core	64 MB	2.0

External links

• HP's documentation - page down for PA-RISC, Architecture PDFs available.
• OpenPA.net Comprehensive PA-RISC chip and computer information.
• PA-RISC Linux Homepage for the PA-RISC Linux port.
• The1 shells Free shell access to a Debian Linux PA-RISC system.
• A few words about the PA-RISC-based HP-9000, its unique HP Color Recovery technology, and NEXTSTEPde:PA-RISC

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