Latch
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- A latch is a type of door or window lock (device). A latching relay is a relay with two stable positions.
A latch is an electronic circuit used to store information in asynchronous sequential logic systems. One latch can store one bit of information. Latches often occur in multiples, some of which have special names, such as the 'quad latch' (which can store four bits) and the 'octal latch' (eight bits). Latches are devices which have no clock input and change output state only in response to data input, while flip-flops have data inputs but change output state only in response to a clock input.
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SR latch
Image:SR-NOR-latch.pngThe logically simplest latch is the SR latch, where S and R stand for 'set' and 'reset'. The latch is constructed from a pair of cross-coupled NOR (negative OR) logic gates. The stored bit is present on the output marked Q.
Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns low. On the other hand, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns low. The output of the latch cannot be predicted if S and R are brought high at the same time, so this condition must be avoided.
| SR latch truth table | ||||
|---|---|---|---|---|
| S | R | Q | Qnext | Comment |
| 0 | 0 | 0 | 0 | Maintain |
| 0 | 0 | 1 | 1 | Maintain |
| 0 | 1 | 0 | 0 | Reset |
| 0 | 1 | 1 | 0 | Reset |
| 1 | 0 | 0 | 1 | Set |
| 1 | 0 | 1 | 1 | Set |
| 1 | 1 | 0 | - | Not allowed |
| 1 | 1 | 1 | - | Not allowed |
SR latch
Image:Sr-latch.pngAnother simple latch is the SR latch, where S and R stand for 'not set' and 'not reset'. This is constructed from a pair of cross-coupled NAND (negative AND) logic gates. NAND gates tend to be more compact than NOR gates in integrated circuits, so this variety is more common, despite the notational inconvenience of its active-low inputs.
Operation is similar to that of the SR latch, except that the S and R inputs are now active-low instead of active-high.
| SR latch truth table | ||||||
|---|---|---|---|---|---|---|
| S | R | S | R | Q | Qnext | Comment |
| 0 | 0 | 1 | 1 | 0 | 0 | Maintain |
| 0 | 0 | 1 | 1 | 1 | 1 | Maintain |
| 0 | 1 | 1 | 0 | 0 | 0 | Reset |
| 0 | 1 | 1 | 0 | 1 | 0 | Reset |
| 1 | 0 | 0 | 1 | 0 | 1 | Set |
| 1 | 0 | 0 | 1 | 1 | 1 | Set |
| 1 | 1 | 0 | 0 | 0 | - | Not allowed |
| 1 | 1 | 0 | 0 | 1 | - | Not allowed |
Gated D Latch
A gated D latch is a latch constructed from an SR latch, two additional AND gates, a NOT gate, and two inputs, data (<math>D</math>) and gate (<math>G</math>). The S input is set to D AND G, while the R input is set to <math>\bar D</math> AND G. When G is set to low (0), output does not change (in other words, Qnext equals Q). When G is set to high (1), output (Q) is equal to D.
| Gated D latch truth table | ||||
| G | D | Q | Qnext | Comment |
| 0 | 0 | 0 | 0 | No change |
| 0 | 0 | 1 | 1 | No change |
| 0 | 1 | 0 | 0 | No change |
| 0 | 1 | 1 | 1 | No change |
| 1 | 0 | 0 | 0 | Set data |
| 1 | 0 | 1 | 0 | Set data |
| 1 | 1 | 0 | 1 | Set data |
| 1 | 1 | 1 | 1 | Set data |