VIA C3
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The VIA C3 is an x86 central processing unit for personal computers produced by VIA Technologies. Although the predecessor to the VIA C3 was called the "VIA Cyrix III," both it and the VIA C3 are based on the CPU design technology of Centaur Technology, makers of the WinChip C6. VIA bought Centaur from IDT.
As of March 2004 the fastest edition currently available works at the speed of 1.4 GHz with a 133 MHz front side bus on a Socket 370 motherboard or factory soldered EBGA on Mini-ITX mainboards. Both fanless and fan-cooled versions are available at 1 GHz. Fan cooled versions are available at 1.3 GHz.
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Core development
VIA purchased the rights to Cyrix chips, but their C3 CPU was based upon the old WinChip (Centaur) core. A half speed FPU and absence of L2 cache led to poor performance. It was only with a release of the C5X (Nehemiah) that the numerous design shortcomings of the Winchip core, including incomplete MMX compatibility, were properly addressed.
In the C5XL Nehemiah VIA introduced hardware security features aimed at the embedded marketspace:
- Twin hardware random number generators. (These generators are erroneously called “quantum-based” in VIA's marketing literature. The detailed analysis of the generator makes clear that the source of randomness is thermal, not quantum.)
Extended in the C5P Nehemiah:
- High performance AES encryption in hardware
- A Ball grid array package the size of a 1 cent coin.
The C7 is a tweaked version of the C3, with the major change being a move to a 90 nm SOI manufacturing process developed by IBM Microelectronics, at East Fishkill in New York State. The chip was designed by the old Centaur team in Austin, Texas, by a permanent staff of a mere 85 engineers, or so. New Features include:
- 2GHz operation and a low TDP of 20 watts. For comparison, Dothan-core Pentium M processors need 27 watts to reach 2.0 GHz.
- Support for SSE2 and SSE3 extended instructions.
- Hardware support for SHA-1 and SHA-256 hashing.
- Hardware based "Montgomery Multiplier" supporting key sizes up to 32K for public key cryptography
- NX flag to reduce buffer overflows and guard against viral attacks
- "Twin Turbo" technology, which consists of dual PLLs, one set at a high clock speed and the other set at a lower speed. This allows the processor's clock frequency to be adjusted in one processor cycle to reduce power consumption in a fashion similar to the SpeedStep technology found in Pentium M processors.
Processor table
| Processor | Speed (MHZ) | FSB (MHZ) | L1 cache | L2 cache | FPU Speed | Pipeline Stages | Max TDP (W) | Core (V) | Process (nm) |
|---|---|---|---|---|---|---|---|---|---|
| C5A (Samuel) | 500-667 | 100/133 | 128 | 0 | 50% | 12 | 8.5 | 1.9-2.0 | 180 Al |
| C5B (Samuel2) | 700-800 | 100/133 | 128 | 64 | 50% | 12 | 12 | 1.6-1.65 | 150 AL |
| C5C (Ezra-T) | 800-950 | 100/133 | 128 | 64 | 50% | 12 | 15 | 1.35 | 150/130 Al |
| C5M (Ezra-T) | 800-950 | 100/133 | 128 | 64 | 50% | 12 | 15 | 1.35 | 150/130 Cu |
| C5N (Ezra-T) | 800-950 | 100/133 | 128 | 64 | 50% | 12 | 15 | 1.35 | 130 Cu |
| C5X (Nehemiah) | 1-1.4Ghz | 133 | 128 | 64 | 100% | 16 | 20 | 1.4-1.45 | 130 Cu |
| C5XL (Nehemiah) | 1-1.4Ghz | 133 | 128 | 64 | 100% | 16 | 20 | 1.4-1.45 | 130 Cu |
| C5P (Nehemiah) | 1-1.4Ghz | 133 | 128 | 64 | 100% | 16 | 20 | 1.4-1.45 | 130 Cu |
| C7-M (Esther C5-J) | 1.5-2.0Ghz | 400/533 | 128 | 128 | 100% | 16 | 20 | 0.9-1.1 | 90 SOI |
| C7 (Esther C5-J) | 1.5-2.0Ghz | 800 | 128 | 256 | 100% | 16 | 20 | 0.9-1.1 | 90 SOI |
Roadmap changes
According to VIA, the VIA C3 was to be superseded in 2003 by the VIA C4 - a clone of the Intel Pentium 4 processor. The VIA C4 naming was supposedly skipped because C4 is a high explosive. In September 2004 VIA announced a change of naming policy, placing all their processors in the C3 or C7 category, with an M suffix for mobile devices. The C5P (Nehemiah) is now marketed as the C3 processor, most typically sold at 1.2 GHz. At one time the VIA roadmap predicted 3 GHz by Q4 2003 based upon the C4.
Comparative die size
| Processor | Secondary Cache (k) | Die size 130 nm (mm²) | Die size 90 nm (mm²) |
|---|---|---|---|
| C3 / C7 | 64/128 | 52 | 30 |
| Athlon XP | 256 | 84 | N/A |
| Athlon 64 | 512 | 144 | 84 |
| P4 Northwood | 512 | 146 | N/A |
| P4 Prescott | 1024 | N/A | 110 |
NOTE: Even the 180 nm Duron Morgan core (106 mm²) with a mere 64 K secondary cache, when shrunk down to a 130 nm process, would have still had a die size of 76 mm². The VIA x86 core is clearly the smallest and cheapest to produce. As can bee seen in this table, four C7 cores could be manufactured for the same cost as a single core P4 on 90 nm process.
Design methodology
While being slower than x86 CPUs being sold by AMD and Intel, both in absolute terms and on a clock for clock basis, VIA's chips are much smaller, cheaper to manufacture, and lower power. This makes them highly attractive in the embedded market space, and increasingly in the mobile sector as well.
This has also enabled VIA to continue to scale the frequencies of their chips, with each manufacturing process die shrink, while competitive products from Intel (such as the P4 Prescott) have encountered severe thermal management issues.
To this extent, the performance gap that used to exist between VIA and competing x86 chips is starting to narrow. Some of the design trade offs made by the VIA design team are worthy of study, as they run contrary to accepted wisdom.
- Because memory performance is the limiting factor in many benchmarks, VIA processors implement large primary caches, large TLBs, and aggressive prefetching, among other enhancements. While these features are not unique to VIA, memory access optimization is one area where they have not dropped features to save die space. In fact generous primary caches (128K) have always been a distinctive hallmark of Centaur / VIA designs.
- Clock frequency is in general terms favored over increasing instructions per cycle. Complex features such as out-of-order instruction execution are deliberately not implemented, because they impact the ability to increase the clock rate, require a lot of extra die space and power, and have little impact on performance in several common application scenarios. Internally, the C7 has 16 pipeline stages.
- The pipeline is arranged to provide one-clock execution of the heavily used register–memory and memory–register forms of x86 instructions. Several frequently used instructions require fewer pipeline clocks than on other x86 processors.
- Infrequently used x86 instructions are implemented in microcode and emulated. This saves die space and reduces power consumption. The impact upon the majority of real world application scenarios is minimized.
These design guidelines are startlingly reminiscent of those advocated by the original RISC advocates, who stated a smaller set of instructions, better optimized, would deliver faster overall CPU performance. We may therefore see RISC design values, having already heavily influenced development of the Athlon and Pentium 4 architectures, coming once again back into favor, as thermal considerations top out processor speed, and force design compromises, over brute force.
Contracts
VIA’s embedded platform products have reportedly (2005) been adopted in Nissan’s car series, the Lafesta, Murano, and Presage. These and other high volume industrial applications are starting to generate big profits for VIA as the small form factor and low power advantages close embedded deals.