Programmable array logic
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Image:MMI PAL 16R6.jpg Programmable array logic (PAL) is a programmable logic device used to implement combinational logic circuits. Monolithic Memories, Inc. (MMI) introduced the PAL in the mid 1978. The project to create the PAL device was managed by John Birkner and the actual PAL circuit was designed by H. T. Chua.
It was not the first commercial programmable logic device, Signetics had been selling their field programmable logic array (FPLA) since 1975. These devices were completely unfamiliar to most circuit designers and were perceived to be too difficult to use. The FPLA had a relatively slow maximum operating speed (due to both a programmable AND array and OR array), was expensive, and had a poor reputation for testability. Another factor limiting the acceptance of the FPLA was the large package, a 28 pin DIP 600 mils wide.
In a previous job Birkner had developed a 16-bit processor using 80 standard logic devices. His experience with standard logic led him to believe that user programmable devices would be more attractive to users if the devices were designed to replace standard logic. This meant that the package sizes had to be more typical of the existing devices, and the speeds had to be improved. The PAL met these requirements and was a huge success and were second sourced by National Semiconductor, Texas Instruments, and Advanced Micro Devices.
Image:Programmable Logic Device.jpg
Early PALs were 20-pin DIP (dual inline package) components fabricated in bipolar silicon transistor technology with nichrome programming fuses. The 16L8 and 16R8 were popular members of the product family. The devices have fixed-or, programmable-and-plane arrays of transistor cells to implement 'sum-of-products' binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback from the outputs. Before PALs were introduced digital designers would use SSI (small-scale integration) components, such as 7400 series nand gates and D-flipflops. One PAL device would typically replace dozens of such 'discrete' logic packages, so the SSI business went into decline as the PAL business took off. PALs were used advantageously in many products, such as minicomputers, as documented in the best-selling book "The Soul of a New Machine."
PAL Architectures
The early 20 pin PALs had 10 inputs and 8 outputs. The outputs were active low and could be registered or combinational. The PAL16L8 had 8 combinational outputs and the PAL16R8 had 8 registered outputs. The PAL16R6 had 6 registered and 2 combinational while the PAL16R4 had 4 of each. Each output had 8 product terms (AND gates), however the combinational outputs used one of the terms to control a bidirectional output buffer. There were other combinational that have fewer outputs with more product term per output and were available with active high outputs. The 16X8 family or registered devices had an XOR gate before the register. There was also a 24 pin versions of these PALs.
Each member of the PAL family was configured during manufacturing. You could not get 5 registered outputs with 3 active high combinational outputs. In 1983 AMD introduced the 22V10, a 24 pin device with 10 output macrocells. Each macrocell could be configured by the user to be combinational or registered, active high or active low. The number of product term allocated to an output varied from 8 to 16. This one device replace all of the 24 pin fixed function PAL devices.
 PAL 16R4 Block Diagram |
 AMD 22V10 Output Macrocell |
 AMD 22V10 Block Diagram |
 AMD 22V10 in 24-pin DIP |
PALASM
Image:PALASM Design.jpg Early PALs were programmed using PALASM language files (converted by a compiler into JEDEC ASCII/hexadecimal files) and a special electronic programming system available from either the manufacturer or a third-party, such as DATA/IO. Gang programmers were used when more than just a few parts were needed and for large volumes the manufacturer would fabricate a custom metal mask for manufacturing so electrical programming could be eliminated to reduce cost. PALASM was used to express boolean equations for the outputs pins in a text file which was then converted to the 'fuse map' file for the programming system using a vendor-supplied program; later the option of translation from schematics became common, and later still, 'fuse maps' could be 'synthesized' from an HDL (hardware description language,) such as Verilog.
Other Devices
After MMI succeeded with the 20-pin PAL parts, AMD introduced the 24-pin 22V10 PAL with additional features. After buying out MMI (1987?), AMD spun off a consolidated operation as Vantis, and that business was acquired by Lattice Semiconductor in 1999.