EM64T

From Free net encyclopedia

Extended Memory 64-bit Technology (EM64T) is Intel's implementation of AMD64, a 64-bit extension to the IA-32 architecture. See the AMD64 article for architectural details.

1 History
2 Intel CPUs with EM64T
3 Differences between AMD64 and EM64T
4 See also
5 External links

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History

The history of the EM64T project is long and convoluted, mainly due to the internal politics of Intel. It began with the codename Yamhill, named after the Yamhill River in Oregon's Willamette Valley. After several years of denying that this project existed, Intel eventually admitted it existed in early 2004, and gave it the codename CT (Clackamas Technology), also named after an Oregon river (the Clackamas River, also a tributary of the Willamette River). Then within the space of weeks of the CT announcement, Intel gave it several new names. After the spring 2004 IDF, Intel named it IA-32E (IA-32 Extensions) and a few weeks later devised the name EM64T. Intel's chairman at the time, Craig Barrett, admitted that this was one of their worst kept secrets.

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Intel CPUs with EM64T

EM64T was originally implemented on the E revision (Prescott) of Pentium 4 line of microprocessors, which were supported by i915P (Grantsdale) and i925X (Alderwood) chipsets in June of 2004. EM64T's implementation was largely due to the competitive pressure of Advanced Micro Devices AMD64 technology implemented on Opteron and Athlon64 lines of microprocessing units, otherwise known as the K8 core, one year earlier in 2003; and the technology was largely built compatible to AMD64, and the then announced Windows XP 64 bit Edition supporting AMD64 technology. Intel's first processor to activate the EM64T technology was the multi-socket processor Xeon codenamed Nocona. Since the Xeon itself is directly based on Intel's desktop processor, the Pentium 4, the Pentium 4 also has EM64T technology built in, although as with Hyper-Threading, this feature was not initially enabled on the then-new Prescott design, likely because Intel had not yet perfected it at the time. Intel has since begun selling EM64T enabled Pentium 4s using the E0 revision of the Prescott core, being sold on the market as the Pentium 4, model F. The E0 revision also adds eXecute Disable(XD) support to EM64T, Intel's name for the NX bit, and has been included in the current Xeon codenamed Irwindale. All 8xx/6xx/5x6/5x1/3x6/3x1 series CPUs have EM64T enabled, as will all future Intel CPUs.

As of March 2006, none of Intel's notebook CPUs (Core Duo, Pentium M, Celeron M, Mobile Pentium 4) supports EM64T. The first Intel mobile processor supporting EM64T will be the dual core Merom, which is scheduled to be released in the fourth quarter of 2006.

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Differences between AMD64 and EM64T

There are a small number of differences between each instruction set. Compilers generally produce binaries that target both AMD64 and EM64T, making the differences mainly of interest to compiler developers and operating system developers.

Early AMD64 processors lacked the CMPXCHG16B instruction, which is an extension of the CMPXCHG8B instruction present on most post-486 processors. Similar to CMPXCHG8B, CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for high resolution counters that could be updated by multiple processors (or cores). Without CMPXCHG16B the only way to perform such an operation is by using a critical section.

Early Intel CPUs with EM64T lacked LAHF and SAHF instructions supported by AMD64 until introduction of Pentium 4 G1 step in December 2005. LAHF and SAHF are load/store instructions for status flags.

Early Intel CPUs with EM64T also lack the NX bit (No Execute bit) of the AMD64 architecture. The NX bit marks memory pages as non-executable, allowing protection against many types of malicious code.

SYSCALL and SYSRET are also only supported in IA-32e mode (not in compatibility mode) on EM64T. SYSENTER and SYSEXIT are supported in both modes.

Near branches with the 0x66 (operand size) prefix behave differently. One type of CPU clears only the top 32 bits, while the other type clears the top 48 bits.

EM64T's BSF and BSR instructions act differently when the source is 0 and the operand size is 32. The processor sets the zero flag and leaves the upper 32 bits of the destination undefined.

EM64T lacks 3DNow! instructions. This includes prefetch with the opcode 0x0F 0x0D and PREFETCHW, which are useful for hiding memory latency.

EM64T lacks the ability to save and restore a reduced (and thus faster) version of the floating-point state (involving the FXSAVE and FXRSTOR instructions).

EM64T lacks some model-specific registers that are considered architectural to AMD64. These include SYSCFG, TOP_MEM, and TOP_MEM2.

EM64T supports microcode update as in 32-bit mode.

EM64T's CPUID instruction is very vendor-specific, as is normal for x86-style processors.

The MONITOR and MWAIT instructions, used by operating systems to better deal with Hyper-threading, are only supported (and only useful) on EM64T.

AMD64 systems allow the use of the AGP aperture as an IO-MMU. Operating systems can take advantage of this to let normal PCI devices DMA to memory above 4 GB. EM64T systems require the use of bounce buffers, which are slower.

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