AMD64

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Image:30436A 64 E RGB.gif AMD64 (also x86-64 or x64) is a 64-bit microprocessor architecture and corresponding instruction set designed by Advanced Micro Devices. It is a superset of the x86 architecture, which it natively supports. The AMD64 instruction set is currently implemented in AMD's Athlon 64, Athlon 64 FX, Athlon 64 X2, Turion 64, Opteron and later Sempron processors. In an ironic twist of computing history, it has been adopted (under the name EM64T or IA-32e) by Intel—the original creators of the x86 processor line—in its newer Pentium 4, Pentium D, Pentium Extreme Edition, Celeron D, and Xeon processors. Microsoft's marketing instead used the term x64.

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Architecture Features

AMD's x86-64 instruction set (later renamed AMD64) is an extension of Intel's IA-32 (x86-32) architecture. The primary defining characteristic of AMD64 is its support for 64-bit general purpose registers, 64-bit integer arithmetic and logical operations, and 64-bit virtual addresses. The designers took the opportunity to make other improvements as well. The most significant changes include:

  • Full support for 64-bit integers: All general-purpose registers (GPRs) are expanded from 32 to 64 bits, and all arithmetic and logical operations, memory-to-register and register-to-memory operations, etc., are now directly supported for 64-bit integers. Pushes and pops on the stack are always in eight-byte strides, and pointers are eight bytes wide.
  • Additional registers: In addition to increasing the size of the general-purpose registers, their number is increased from 8 in x86-32 to 16. There is therefore less need to save registers, restore registers, and generally manage registers to cope with a shortage of register space, and most arguments to most procedures can be passed in registers rather than on the stack. This should be a significant area of speed improvement once optimized applications appear, especially for software with computationally-intensive deeply-nested loops. This addresses one of the most outstanding deficiencies of x86-32. However, AMD64 still has fewer registers than many common RISC processors which often have 32 registers, as well as the IA-64 architecture which has 128.
  • Additional XMM registers: Similarly, the number of 128-bit XMM registers (used for Streaming SIMD instructions) is also increased from 8 to 16.
  • Larger virtual address space: Current processor models implementing the AMD64 architecture can address up to 256 tebibytes of virtual address space (248 bytes). This limit can be raised in future implementations to 16 exbibytes (264 bytes). This is compared to just 4 gibibytes for 32-bit x86.
  • Larger physical address space: Current implementations of the AMD64 architecture can address up to 1 tebibyte of RAM (240 bytes); the architecture permits extending this to 4 pebibytes (252 bytes) in the future (limited by the page table entry format). In legacy mode, Physical Address Extension (PAE) is supported, as it is on most current 32-bit x86 processors, allowing access to a maximum of 64 gibibytes.
  • Instruction pointer relative data access: Instructions can now reference data relative to the instruction pointer (RIP register). This makes position independent code, as is often used in shared libraries and code loaded at run time, more efficient.
  • SSE instructions: The original AMD64 architecture adopted Intel's SSE and SSE2 as core instructions. SSE3 instructions were added in April 2005. SSE2 replaces the x87 instruction set's IEEE 80-bit precision, with the choice of either IEEE 32-bit or 64-bit floating-point math. This provides floating-point operations compatible with many other modern CPUs. The SSE and SSE2 instructions have also been extended to support the eight new XMM registers. SSE and SSE2 are available in 32-bit mode in modern x86 processors; however, if they're used in 32-bit programs, those programs will only work on systems with processors that support them. This is not an issue in 64-bit programs, as all processors that support AMD64 support SSE and SSE2, so using SSE and SSE2 instructions instead of x87 instructions doesn't reduce the set of machines on which the programs will run. Since SSE and SSE2 are generally faster than, and duplicate most of the features of, the traditional x87 instructions, MMX, and 3DNow!, the latter are redundant under AMD64.
  • No-Execute bit: The “NX” bit (bit 63 of the page table entry) allows the operating system to specify which pages of virtual address space can contain executable code and which cannot. An attempt to execute code from a page tagged "no execute" will result in a memory access violation, similar to an attempt to write to a read-only page. This should make it more difficult for malicious code to take control of the system via "buffer overrun" or "unchecked buffer" attacks. A similar feature has been available on x86 processors since the 80286 as an attribute of segment descriptors, however this works only on an entire segment at a time. Segmented addressing has long been considered an obsolete mode of operation, and all current PC operating systems in effect bypass it, setting all segments to a base address of 0 and a size of 4 GiB. AMD was the first x86-family vendor to support no-execute in linear addressing mode. The feature is also available in legacy mode on AMD64 processors, and recent Intel x86 processors, when PAE is used.
  • Removal of older features: A number of "system programming" features of the x86 architecture are not used in modern operating systems and are not available on AMD64 in long mode. These include segmented addressing (although the FS and GS segments remain in vestigial form, for compatibility with Windows code), the task state switch mechanism, and Virtual-8086 mode. These features do of course remain fully implemented in "legacy mode," thus permitting these processors to run 32-bit and 16-bit operating systems without modification. If, at some point in the future, 32-bit code using those features is no longer used, support for them might be removed from hardware to streamline processor design and save manufacturing costs. These features could be emulated in the operating system to preserve legacy application compatibility.
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Operating modes

Operating mode Operating system required Application recompile required Default address size Default operand size Register extensions Typical GPR width
Long mode 64-bit mode New 64-bit (x86-64) OS (e.g.WinXPx64, Linux x86-64) yes 64 32 yes 64
Compatibility mode no 32 32 no 32
16 16 16
Legacy Mode Protected Mode Legacy 16-bit or 32-bit OS no 32 32 no 32
16 16 16
Virtual 8086 mode 16 16 16
Real mode Legacy 16-bit OS
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Operating mode explanation

There are two primary modes of operation for this architecture:

Long Mode 
The intended primary mode of operation of the architecture; it is a combination of the processor's native 64-bit mode and a 32-bit/16-bit compatibility mode. It is used by 64-bit operating systems. Under a 64-bit operating system, 64-bit, 32-bit and 16-bit (or 80286) protected mode applications may be supported.
Since the basic instruction set is the same, there is no major performance penalty for executing x86 code. This is unlike Intel's IA-64, where differences in the underlying ISA means that running 32-bit code is like using an entirely different processor. However, on AMD64, 32 bit x86 applications may still benefit from a 64-bit recompile, due to the additional registers in 64-bit code, which a high-level compiler can use for optimization.
Legacy Mode 
The mode used by 16-bit (protected mode or real mode) and 32-bit operating systems. In this mode, the processor acts just like an x86 processor, and only 16-bit or 32-bit code can be executed. 64-bit programs will not run.
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Market analysis

AMD64 represents a break with AMD's past behavior of following Intel's standards, but repeats Intel's earlier behavior of extending the x86 architecture, from the 16-bit 8086 to the 32-bit 80386 and beyond, without ever removing backwards compatibility.

It was believed at one point that 64-bit RISC chips such as the DEC Alpha would eventually replace the outdated and quirky x86 architecture. Part of the reason this did not happen was the vast investment in application software for x86 systems. AMD64 effectively migrates the x86 architecture into a fully 64-bit environment, while maintaining legacy compatibility with x86 applications.

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Operating System Support

The following operating systems and releases support the AMD64 architecture in long mode.

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DOS

It is possible to enter Long mode under DOS with a DOS Extender similar to DOS4GW. DOS itselves is not aware of that and no benefits should be expected unless running DOS in an emulation with an adequate virtualisation driver backend e.g. for the mass storage interface.

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FreeBSD

FreeBSD/amd64 is a Tier 1 platform, being first added as an experimental architecture in 5.1-RELEASE. 6.0-RELEASE cleaned up some quirks with running 32-bit executables under amd64, and most drivers work just as they do on i386. Work is currently being done for fully integrating the i386 ABI, in the same manner as the linux ABI currently works.

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Linux

Recent releases of the Linux kernel (v2.6 as of this writing) can be built natively in long mode, supporting AMD64 and EM64T, with backwards compatibility for loading 32-bit executables and emulating the 32-bit system call API. This permits programs to be recompiled into long mode while retaining the use of 32-bit programs. Gentoo, Novell, SuSE, Fedora, Mandriva, Red Hat, CentOS, Ubuntu and PLD Linux distributions currently ship with AMD64-native kernels and userlands. Debian currently has an unofficial "stable" version, as well as "testing" and "unstable" flavours.

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Mac OS X

AMD64 CPUs are recognized by hacked versions of Mac OS X "for Intel." A patch is needed to emulate SSE3 instructions on the earlier AMD64 chips that support only SSE2.

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MenuetOS

The AMD64 version of MenuetOS was released in June 2005. Although Menuet was originally written for 32-bit x86 architectures and released under the GPL, the AMD64 version is proprietary. It is distributed as freeware without the source code for core components.

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NetBSD

Support for AMD64 was first committed to the NetBSD source tree on June 19th, 2001. As of NetBSD 2.0, released on December 9th, 2004, NetBSD/amd64 is a fully integrated and supported port.

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OpenBSD

OpenBSD has supported AMD64 since OpenBSD 3.5, released on May 1st, 2004. Complete in-tree support for the platform was achieved prior to the hardware's initial release due to AMD's loaning of several machines for the project's hackathon that year. OpenBSD developers have taken to the platform because of its use of the NX bit, which allowed for an easy implementation of the W^X feature.

The code for the AMD64 port of OpenBSD also runs on the Intel processors with EM64T support which contain cloned support for the AMD64 extensions, but since Intel left out support for the page table NX bit in early EM64T processors, there is no W^X support on those Intel CPUs; later Intel EM64T processors added support for the NX bit under the name "XD bit". SMP is supported on OpenBSD's AMD64 port, starting with release 3.6 on November 1st, 2004.

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Solaris

Solaris has supported AMD64 since Solaris 10.

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Windows

x64 editions of Windows client and server, Windows XP Professional x64 Edition and Windows Server 2003 SP1 x64 Edition, were released in March 2005. Internally they are actually the same build (5.2.3790.1830 SP1), as they share the same source base and operating system binaries, so even system updates are released in unified packages, much in the manner of Windows 2000 Professional and Server editions for x86. Windows for x64 has the following characteristics:

  • 8 tebibytes (243 bytes) of user mode virtual address space per process. A 64-bit program can use all of this, subject of course to backing store limits on the system. This is a 4096-fold increase over the default 2 gibibyte user-mode virtual address space offered by 32-bit Windows.
  • 8 tebibytes (243 bytes) of kernel mode virtual address space for the operating system. Again, this is a 4096-fold increase over 32-bit Windows versions. The increased space is primarily of benefit to the file system cache and kernel mode "heaps" (nonpaged pool and paged pool).
  • Support for up to 128 GiB (Windows XP) or 1 TiB (Windows Server 2003) of RAM.
  • LLP64 data model: "int" and "long" types are still 32 bits wide, while pointers and types derived from pointers are 64 bits wide.
  • Device drivers and system services must be 64-bit versions; there is no support for running 32-bit kernel-mode executables within the 64-bit OS.
  • Support for running existing 32-bit applications (.exe's) and dynamic link libraries (.dll's). A 32-bit program, if linked with the "large address aware" option, can use up to 4 gigabytes of virtual address space, as compared to the default 2 gigabytes (optional 3 gigabytes with /3GB boot.ini option and "large address aware" link option) offered by 32-bit Windows.
  • 16-bit DOS, Windows (Win16), OS/2 and POSIX applications will not run on x64 versions of Windows due to removal of NTVDM.
  • Full implementation of the NX (No Execute) page protection feature. This is also implemented on recent 32-bit versions of Windows when they are started in PAE mode.
  • As in x86 versions of the Windows NT family, the FS and GS segment descriptors are used to point to two operating-system defined structures: the Thread Information Block and Processor Control Region, respectively. Thus, for example, [FS]:0 is the address of the first member of the TIB. Maintaining this convention made the x64 port easier, but required AMD to retain the function of the FS and GS segments in long mode— even though segmented addressing per se is not really used by any modern operating system.
  • Early reports claimed that the operating system scheduler would not save and restore the x87 FPU machine state across thread context switches. Observed behavior shows that this is not the case: the x87 state is saved and restored, except for kernel-mode-only threads. Nevertheless, the most recent documentation available from Microsoft states that the x87/MMX/3DNow! instructions may not be used in long mode.
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Implementations

The following processors implement the AMD64 architecture:

Image:Athlon64.png

The following future processors will implement the AMD64 architecture:

  • Intel Next Generation Microarchitecture (EM64T)
    • "Merom" (codename for upcoming notebook core)
    • "Conroe" (codename for upcoming desktop core)
    • "Woodcrest" (codename for upcoming server/workstation core)
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See also

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External links

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