Sempron
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Image:SempronLogo.pngImage:Sempron-3000.jpg
Sempron is, as of 2005-06, AMD's newest low-end CPU, replacing the seven year old Duron processor and competing against Intel's Celeron D processor.
AMD coined the name from the latin semper, which means always/everyday, with the purpose of stating that Sempron was the right appliance for everyday computing.
The first Semprons were based on the Athlon XP architecture using the Thoroughbred/Thorton core. These models were equipped with the Socket-A interface, a 256 KB L2-Cache, and 166 MHz Front side bus (FSB 333). Later, AMD introduced the Sempron 3000+, based on the Barton core (512 KB L2-cache.) From a hardware and user standpoint, the Socket-A Semprons were essentially renamed Athlon-XP desktop CPUs. AMD has ceased production of all Socket-A Semprons.
In the second half of 2005, AMD added 64-bit support (AMD64) to the Socket 754 Sempron line. This revision of chips is often referred to as "Sempron 64" to differentiate it from the previous revision. The term is unofficial and not used by AMD. AMD's intent in releasing a 64-bit low-end processors was to further the market for 64-bit processors, which, at the time of Sempron 64's first release, was a niche market.
As of 2005-06, the current production models (Paris/Palermo core) are based on the architecture of the Socket 754 Athlon 64. Differences from Athlon 64 processors include a reduced cache size (either 128 or 256 KB L2), and the absence of AMD64 support in earlier models. Apart from these differences, the Socket 754 Semprons share most features with the more powerful Athlon 64, including an integrated (on-die) memory controller, the HyperTransport bus, and AMD's "NX bit" feature.
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Models
Thoroughbred B/Thorton (130 nm)
- L1-Cache: 64 + 64 KB (Data + Instructions)
- L2-Cache: 256 KB, fullspeed
- MMX, 3DNow!, SSE
- Socket A (EV6)
- Front side bus: 166 MHz (FSB 333)
- VCore: 1.6 V
- First release: July 28, 2004
- Clockrate: 1500 MHz - 2000 MHz (2200+ to 2800+)
Barton (130 nm)
- L1-Cache: 64 + 64 KB (Data + Instructions)
- L2-Cache: 512 KB, fullspeed
- MMX, 3DNow!, SSE
- Socket A (EV6)
- Front side bus: 166 MHz (FSB 333)
- VCore: 1.6 V
- First release: September 17, 2004
- Clockrate: 2000 MHz (3000+)
Paris (130 nm SOI)
- L1-Cache: 64 + 64 KB (Data + Instructions)
- L2-Cache: 256 KB, fullspeed
- MMX, 3DNow!, SSE, SSE2
- Enhanced Virus Protection (NX bit)
- Integrated DDR1 memory controller
- Socket 754, 800 MHz HyperTransport
- VCore: 1.4 V
- First release: July 28, 2004
- Clockrate: 1800 MHz (3100+)
- Stepping: CG (Part No.: *AX)
Palermo (90 nm SOI)
- Early models (stepping D0) are downlabeled "Oakville" mobile Athlon64
- L1-Cache: 64 + 64 KB (Data + Instructions)
- L2-Cache: 128/256 KB, fullspeed
- MMX, 3DNow!, SSE, SSE2
- SSE3 support on E3 and E6 steppings
- AMD64 on E6 stepping
- Cool'n'Quiet (Sempron 3000+ and higher)
- Enhanced Virus Protection (NX bit)
- Integrated DDR1 memory controller
- Socket 754, 800 MHz HyperTransport
- VCore: 1.4 V
- First release: February 2005
- Clockrate: 1400 - 2000 MHz
- 128 KB L2-Cache (Sempron 2600+, 3000+, 3300+)
- 256 KB L2-Cache (Sempron 2500+, 2800+, 3100+, 3400+)
- Steppings: D0 (Part No.: *BA), E3 (Part No.: *BO), E6 (Part No.: *BX)
Future processors are anticipated to support Intel's new SSE4 and AMD's next-generation 3DNow!.
See also
External links
- AMD K7 Sempron technical specifications
- AMD K8 Sempron technical specifications
- AMD's Desktop Sempron product page
- AMD's Notebook Sempron product page
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