PowerPC

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PowerPC is a RISC microprocessor architecture created by the 1991 Apple-IBM-Motorola alliance, known as AIM. Originally intended for personal computers, PowerPC CPUs have since become popular embedded and high-performance processors as well. PowerPC was the cornerstone of AIM's PReP and Common Hardware Reference Platform initiatives in the 1990s, but the architecture found the most success in the personal computer market in Apple's Macintosh lines from 1994-2006.

PowerPC is largely based on IBM's earlier POWER architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs and operating systems will run on both if some care is taken in preparation.

Image:IBM PowerPC601 PPC601FD-080-2 top.jpg

Contents

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History

The history of the PowerPC begins with IBM's 801 prototype chip of John Cocke's RISC ideas in the late '70s. 801-based cores were used in a number of IBM embedded products, eventually becoming the 16-register ROMP processor used in the IBM RT. The RT had disappointing performance and IBM started the America Project to build the fastest processor on the market. The result was the POWER architecture, introduced with the RISC System/6000 in early 1990.

The original POWER microprocessor, one of the first superscalar RISC implementations, was a high performance, multi-chip design. IBM soon realized that they would need a single-chip microprocessor and to eliminate some POWER processor instructions to scale their RS/6000 line from lower-end to high-end machines, and work on a single-chip POWER microprocessor, called the RSC (RISC Single Chip) began. In early 1991 IBM realized that their design could potentially become a high-volume microprocessor used across the industry.

IBM approached Apple with the goal of collaborating on the development of a family of single-chip microprocessors based on the POWER architecture. Soon after, Apple, as one of Motorola's largest customers of desktop-class microprocessors, asked Motorola to join the discussions because of their long relationship, their more extensive experience with manufacturing high-volume microprocessors than IBM and to serve as a second source for the microprocessors. This three-way collaboration became known as AIM alliance, for Apple, IBM, Motorola.

To Motorola, POWER looked like an unbelievable deal. It allowed them to sell a widely tested and powerful RISC CPU for little design cash on their own part. It also maintained ties with an important customer, Apple, and seemed to offer the possibility of adding another in IBM who might buy smaller versions from them instead of making their own.

At this point Motorola already had its own RISC design in the form of the 88000 which was doing poorly in the market. A likely reason was that the Motorola chips were consistently late to market due to poor design methodology and manufacturing issues, so late they lost their window of opportunity to be viable competitors to designs like the MIPS and SPARC which beat the 88000 to market.

However, the 88000 was already in production; Data General was shipping 88k machines and Apple already had 88k prototype machines running. If the new POWER single-chip solution could be made bus-comparable at a hardware level with the 88000, that would allow both Apple and Motorola to bring machines to market much faster since they would not have to redesign their board architecture.

The result of these various requirements was the PowerPC (Performance Computing) specification. Everyone seems to have won:

  • IBM got the merchant semiconductor market they were looking for
  • Apple got to use one of the most powerful RISC CPUs on the market, and massive press buzz due to IBM's name
  • Motorola got an up-to-date RISC chip, and help with design methodology from IBM

When the first PowerPC products reached the market, they were met with enthusiasm. In addition to Apple, both IBM and the Motorola Computer Group offered systems built around the processors. Microsoft created a version of Windows NT for the architecture, which was used in Motorola's PowerPC servers, and Sun Microsystems offered a version of its Solaris OS. IBM ported its AIX Unix and planned a release of OS/2. Throughout the mid-1990s, PowerPC processors achieved Benchmark test scores that matched or exceeded those of the fastest x86 CPUs.

Ultimately, demand for the new architecture on the desktop never truly materialized. Windows, OS/2 and Sun customers, faced with the lack of application software for the PowerPC, almost universally ignored the chip. The PowerPC versions of Solaris, OS/2, and Windows were discontinued after only a brief period on the market. Only on the Macintosh, due to Apple's persistence, did the PowerPC gain traction. To Apple, the performance of the PowerPC was a bright spot in the face of increased competition from Windows 95 and Windows NT-based PCs.

However, toward the close of the decade, the same manufacturing issues began plaguing the AIM alliance in much the same way it did Motorola with consistently pushed back deployments of new processors for Apple and other vendors: first from Motorola in the 1990s with the G3 and G4 processors, and IBM with the 64-bit G5 processor in 2003. In 2004, Motorola exited the chip manufacturing business by spinning off its processor business as an independent company called Freescale Semiconductor. Around the same time, IBM exited the personal computer market completely by selling its line of PC products (which used Intel processors) to Chinese computer manufacturer Lenovo and focused their chip designs for PowerPC CPUs towards game machine makers such as the Nintendo Revolution, Sony's PlayStation 3 and Microsoft's Xbox 360. In 2005 Apple announced they would no longer use PowerPC processors in their Apple Macintosh computers, favoring Intel produced processors instead, citing the performance limitations of the chip for future personal computer hardware specifically related to heat generation and energy usage in future products, as well as the inability of IBM to move the 970 (PowerPC G5) processor to the 3 GHz range. This was considered a public relations problem for IBM, since the decision was made in part by their inability to match Intel and other competitors in terms of speed and architecture improvements. This effectively ended the AIM alliance with IBM continuing to use and evolve the PowerPC processor on game consoles and Freescale Semiconductor focusing solely on embedded devices.

This left the future of the PowerPC platform on anything other than embedded devices in much doubt. However, the original POWER architecture IBM developed and from which the PowerPC processor was originally derived was still very much alive on their server offerings for large businesses and continues to evolve to this day (and current POWER processors implement the full PowerPC instruction set architecture).

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Design features

The PowerPC is designed along RISC principles, and allows for a superscalar implementation. Versions of the design exist in both 32-bit and 64-bit implementations. Starting with the basic POWER specification, the PowerPC added:

  • Support for operation as in both big-endian and little-endian modes; the PowerPC can switch from one mode to the other at run-time (see below). This feature is not supported in the PowerPC G5. (This was the reason Virtual PC took so long to be made functional on G5-based Macintoshes.)
  • Single-precision forms of some floating point instructions, in addition to double-precision forms
  • Additional floating point instructions at the behest of Apple
  • A complete 64-bit specification, which is backward compatible with the 32-bit mode
  • Removal of some of the more esoteric POWER instructions, some of which could be emulated by the operating system if necessary.
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Endian-modes

Some of IBM's embedded PowerPC chips use a per-page endianness bit. None of the following applies to them.

Most PowerPC chips switch endianness via a bit in the MSR register, with a second bit provided to allow the OS to run with a different endianness. Accesses to the "inverted page table" (a hash table that functions as a TLB with off-chip storage) are always done in big-endian mode. The processor starts in big-endian mode.

In little-endian mode, the three lowest-order bits of the effective address are exclusive-ORed with a three bit value selected by the length of the operand. This is enough to appear fully little-endian to normal software. An operating system will see a warped view of the world when it accesses external chips such as video and network hardware. Fixing this warped view of the world requires that the motherboard perform an unconditional 64-bit byte swap on all data entering or leaving the processor. Endianness thus becomes a property of the motherboard. An OS that operates in little-endian mode on a big-endian motherboard must both swap bytes and undo the exclusive-OR when accessing little-endian chips.

AltiVec operations, despite being 128-bit, are treated as if they were 64-bit. This allows for compatibility with little-endian motherboards that were designed prior to AltiVec.

An interesting side-effect of this implementation is that a program can store a 64-bit value (the longest operand format) to memory while in one endian mode, switch modes, and read back the same 64-bit value without seeing a change of byte order. This will not be the case if the motherboard is switched at the same time.

Mercury Computer Systems and Matrox ran the PowerPC in little-endian mode. This was done so that PowerPC devices serving as co-processors on PCI boards could share data structures with host computers based on x86. Both PCI and x86 are little-endian. Solaris and Windows NT for PowerPC also ran the processor in little-endian mode.

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Implementations

The first single-chip implementation of the design was the MPC601, released in 1992, based on the RSC, implementing a hybrid of the POWER1 and PowerPC specifications. This allowed the chip to be used by IBM in their existing POWER1 based platforms, although it also meant some slight pain when switching to the 2nd generation "pure" PowerPC designs. Apple continued work on a new line of Macintosh computers based on the chip, and eventually released them as the 601-based Power Macintosh on March 14, 1994.

IBM also had a full line of PowerPC based desktops built and ready to ship; unfortunately, the operating system which IBM had intended to run on these desktops—Microsoft Windows NT—was not complete by early 1993, when the machines were ready for marketing. Accordingly, and further because IBM had developed animosity toward Microsoft, IBM decided to rewrite OS/2 for the PowerPC. It took IBM two years to rewrite OS/2 for PowerPC, and by the time the operating system was ready, the market for OS/2 on PowerPC had evaporated. For this reason, the IBM PowerPC desktops did not ship, although the reference design (codenamed Sandalbow) based on the PowerPC 601 CPU was released as an RS/6000 model (Byte magazine 's April 1994 issue included an extensive article about the Apple and IBM PowerPC desktops).

Apple, who also lacked a PowerPC based OS, took a different route. They rewrote the essential pieces of their Mac OS operating system for the PowerPC architecture, and further wrote a 680x0 emulator that could run 68K based applications and the parts of the OS that had not been rewritten.

The second generation was "pure" and included the "low end" 603 and "high end" 604. The 603 is notable due to its very low cost and power consumption. This was a deliberate design goal on Motorola's part, who used the 603 project to build the basic core for all future generations of PPC chips. Apple tried to use the 603 in a new laptop design but was unable to due to the small 8KB level 1 cache. The 68000 emulator in the Mac OS could not fit in 8KB and thus slowed the computer drastically. The 603e solved this problem by having a 16KB L1 cache which allowed the emulator to run efficiently.

In 1993, developers at IBM's Burlington, Vermont facility started to work on a version of the PowerPC that would support the Intel x86 instruction set directly on the CPU. While the work was done by IBM without the support of the AIM alliance, this chip began to be known inside IBM and by the media as the PowerPC 615. However, profitability concerns and performance issues in the switching between the x86 and native PowerPC instruction sets resulted in the project being canceled in 1995 after only a limited number of chips were produced for in-house testing. However, conflicting reports were made that the switching process in fact took a mere 5 cycles, or the amount of time required for the processor to empty its instruction pipeline, and that Microsoft had a hand in the processor's downfall. [1]

The first 64-bit implementation was the 620, but it appears to have seen little use since Apple didn't want to buy it and with its large die area, was too expensive for the embedded market. It was later and slower than promised, and IBM used their own POWER3 design instead, offering no 64-bit "small" solution until the late-2002 introduction of the PowerPC 970. The 970 is a 64-bit processor derived from the POWER4 server processor. To create it, the POWER4 core was modified to be backwards-compatible with 32-bit PowerPC processors, and a vector unit (similar to the AltiVec extensions in Motorola's 74xx series) was added.

IBM's RS64 processors are a family of chips implementing the "Amazon" variant of the PowerPC architecture. These processors are used in the RS/6000 and AS/400 computer families; the Amazon architecture includes proprietary extensions used by AS/400.

Numerically, the PowerPC is mostly found in controllers in cars. In this role, Freescale Semiconductor has offered up a huge number of versions called the MPC5xx family such as the MPC555, built on a variant of the 601 core called the 8xx designed in Israel by MSIL (Motorola Silicon Israel Limited). The 601 core is single issue, meaning it can only issue one instruction in a clock cycle. To this they add various bits of custom hardware, to allow for I/O on the single chip.

Networking is another area where embedded PowerPC processors are found in large numbers. MSIL took the QUICC engine from the MC68302 and made the PowerQUICC MPC860. This was a very famous processor used in many Cisco edge routers in the late 1990s. Variants of the PowerQUICC include the MPC850, and the MPC823/MPC823e. All variants include a separate RISC microengine called the CPM that offloads communications processing tasks from the central processor and has functions for DMA. The follow-on chip from this family, the MPC8260, has a 603e-based core and a different CPM.

Operating systems used in embedded PowerPC systems include the LynxOS real-time operating system and BlueCat embedded Linux from LynuxWorks. Yellow Dog Linux and PowerPC Linux are also two other flavors of Linux that run on the PowerPC. Apple's Macintosh System 7.1.2 through Mac OS X run on the PowerPC.

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Desktop Computers

Apple is the dominant player in the market of desktop computers based on PowerPC.

There are several attempts to create PowerPC references platform for desktop computers:

  • IBM PReP (PowerPC Reference Platform) is a system standard intended to ensure compatibility among PowerPC-based systems built by different companies. The PReP standard specifies the PCI bus, but will also support ISA, MicroChannel, and PCMCIA. PReP-compliant systems will be able to run OS/2, AIX, Solaris, Taligent, and Windows NT.
  • CHRP (Common Hardware Reference Platform) is an open platform agreed on by Apple, IBM, and Motorola. All CHRP systems will be able to run Mac OS, OS/2-PPC, Windows NT, AIX, Solaris, Novell Netware. CHRP is a superset of PReP and the PowerMac platforms
  • IBM POP (PowerPC Open Platform) is an open and free standard and design of PowerPC motherboards. Unfortunately POP failed because of buggy chip-set.
  • Pegasos ODW (Open Desktop Workstation) is an open and free standard and design of PowerPC motherboards based on Marvell Discovery II (MV64361) chipset.
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Personal Digital Assistant (PDA)

IBM had released a Personal Digital Assistant (PDA) reference platform based on PowerPC 405LP (Low Power).

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Set Top Box (STB)

IBM, Sony, and Zarlink Semiconductor had released several Set Top Box (STB) reference platforms based on IBM PowerPC 405 cores and IBM Set Top Box (STB) System-On-Chip (SOC)

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Design Win summary

PowerPC processors have been used in many products, among which are the following:

Many embedded systems such as:

All three of the major game console manufacturers have announced that their sixth-generation consoles will contain PowerPC-based processors:

  • Sony's PlayStation 3 console, to be released in November 2006, will contain a Cell processor, containing a 3.2 GHz PowerPC control processor, with eight 3.2 GHz closely-coupled DSP-like accelerator processors, seven active and one spare.
  • Microsoft's Xbox 360 console, available now, includes a 3.2 GHz custom IBM PowerPC chip with three symmetrical cores.
  • The Nintendo Revolution console, predicted to ship some time in 2006, is billed as containing a PowerPC-based processor, but technical details have yet to be released.
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Licensees

Companies that have licensed PowerPC include:

and others.

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General-purpose PowerPC processors

PowerPC processors bring the processor's local bus to the chip's surface, and connect to a bridge chip that translate this into other on-board device buses that attach to RAM, PCI, and other devices.

  • 601 MPC601 50 and 66 MHz
  • 602 consumer products (multiplexed data/address bus)
  • 603 notebooks
  • 603e
  • 604
  • 604e
  • 620 the first 64-bit implementation
  • x704 BiCMOS PowerPC implementation by Exponential Technologies
  • 750 (PowerPC G3) (1997) 233 MHz and 266 MHz, 740, 745, 755
  • 7400/7410 (PowerPC G4) (1999) up to 550 MHz, uses AltiVec, a SIMD extension of the original PPC specs
  • 750FX with 512KB L2-Cache announced by IBM in 2001 and available early 2002 at 1 GHz
  • 750GX with 1MB L2-Cache introduced by IBM in 2003
  • 7450 micro-architecture family up to 1.5 GHz and 256KB on-chip L2-Cache and improved Altivec (PowerPC G4)
  • 7447/7457 micro-architecture family up to 1.8 GHz with 512KB on-chip L2-Cache (PowerPC G4)
  • 7448 micro-architecture family in 90nm with 1MB L2-Cache and slightly improved AltiVec (PowerPC G4)
  • 8641 has a processing core that is essentially a 7448, but it also features an embedded memory controller.
  • 8641D is another member of the 7448 based micro-architecture family, featuring two cores and two embedded memory controllers.
  • 970 (PowerPC G5) (2003) A 64-bit implementation derived from the IBM POWER4 enhanced with VMX (AltiVec compatible SIMD extensions) with 512KB L2-Cache operating at speeds of 1.4 GHz, 1.6 GHz, 1.8 GHz, 1.9 GHz, 2.0 GHz, 2.1 GHz, 2.3 GHz, 2.5 GHz and 2.7 GHz
  • 970MP (PowerPC G5) at 1.6-2.5 GHz 2005 with 1MB L2-Cache is the first dual core PowerPC for general use.
  • Gekko 485 MHz (used in the Nintendo GameCube)
  • PA6T-1682M (PWRficient): a dual core PPC running at 2 GHz

In addition, the next generation PowerPC processors, called Power6, is slated to run at clock speeds of 4-5 GHz, and will provide Simultaneous MultiThreading. How it fares on the power consumption front remains to be seen.

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Embedded PowerPC microcontrollers

32-bit PowerPC processors have been a favorite of embedded computer designers. To keep costs low on high-volume competitive products, the CPU core is usually bundled into a system-on-chip (SOC) integrated circuit. SOCs contain the processor core, cache and the processor's local data on-chip, along with clocking, timers, memory (SDRAM), peripheral (network, serial I/O), and bus (PCI, PCI-X, ROM/Flash bus, I2C) controllers. IBM also offers an open bus architecture (called CoreConnect) to facilitate connection of the processor core to memory and peripherals in a SOC design. IBM and Motorola have competed along parallel development lines in overlapping markets. A recent development is the BookE PowerPC Specification, implemented by both IBM and Freescale Semiconductor, which defines embedded extensions to the PowerPC programming model.

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AMCC

  • 440SP: 533-667 MHz, 10/100/1G Ethernet, (2) 64bit PCI-X, 32bit PCI-X, XOR engine, 32k L1 Cache.
  • 440SPe: 533-667 MHz, 10/100/1G Ethernet, (3) 64bit PCI-Express, 64bit PCI-X, XOR engine, 32k L1 Cache.
  • 440EPx: 333-667 MHz, (2) 10/100/1G Ethernet, Hardware Security, PCI, DDR-II, FPU, USB 2.0, 32k L1 Cache.
  • 440GR: 333-667 MHz, (2) 10/100 Ethernet, (4) UART, (2) IIC, 53 GPIO, SPI, 32k L1 Cache.
  • 440GRx: 333-667 MHz, (2) 10/100/1G Ethernet, (4) UART, (2) IIC, 53 GPIO, SPI, DDR-II, Hardware Security, 32k L1 Cache.
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BAE Systems

  • RAD750 radiation hardened CPU based on PowerPC 750 core.
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Culturecom

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IBM (now from AMCC)

  • 401
  • 403: MMU added in most advanced version 403GCX
  • 405: MMU, Ethernet, serial, PCI, SRAM, SDRAM; NPe405 adds more network devices
  • 440xx: A range of processors based on the Book E core.
    • 440EP: 333-667 MHz, (2) 10/100 Ethernet, PCI, DDR, FPU, USB 1.1 & 2.0, 32k L1 Cache.
    • 440GP: 400-500 MHz, (2) 10/100 Ethernet, PCI-X, DDR, 32k L1 Cache.
    • 440GX: 533-800 MHz, (2) 10/100 Ethernet, (2) 10/100/1G Ethernet with TCP/IP hardware acceleration, PCI-X, DDR, 32k L1 Cache
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Motorola (now Freescale)

  • MPC 860/8xx (PowerQUICC): networking & telecomm card controllers
  • MPC 550/5xx line: (8xx core) automotive & industrial controllers
  • MPC 5200/5200B (603e core) automotive & industrial controllers
  • MPC 8260/82xx (PowerQUICC II) a 603 core, networking & telecomm system controllers with high-capacity onchip switched bus
  • MPC 8560/85xx (PowerQUICC III) a PowerPC Book E core, networking & telecomm system controllers with even higher-capacity onchip
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PA Semi

  • PA6T-1682M (PWRficient): a dual core PPC running at 2 GHz (unreleased)
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Xilinx

  • Virtex-II Pro and Virtex-4 FPGA have up to four embedded PowerPC-405 cores.
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References

  • May, Cathy (editor) et.al. (1994). The PowerPC Architecture: A Specification for A New Family of RISC Processors. Morgan Kaufmann Publishers. ISBN 1-55860-316-6 (2nd ed.).
  • Hoxey, Steve (editor) et.al. The PowerPC Compiler Writer's Guide. Warthman Associates. ISBN 0-9649654-0-2.
  • Motorola. Programming Environments Manual for 32-bit Implementations of the PowerPC Architecture. P/N MPCFPE32B/AD .
  • IBM (2000). Book E: Enhanced PowerPC™ Architecture (3rd ed.)
  • Jeff Duntemann and Ron Pronk. (1994) Inside the PowerPC Revolution. Coriolis Group Books, ISBN 1-883577-04-7
  • PowerPC Architecture, an IBM article giving POWER and PowerPC history
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See also

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External links


Image:Motologosmall.png List of Motorola/Freescale microprocessors Image:Freescalelogosmall.png
The 6800 family : 6809 (see also: Hitachi 6309)
68000 family : 68000 | 68008 | 68010 | 68012 | 68020 | 68030 | 68040 | 68060 | ColdFire | DragonBall
Pre-PowerPC RISC : 88000
Floating-point coprocessors : 68881, 68882
PowerPC family (as part of AIM) : PPC 7XX range (aka "PowerPC G3") | PPC 7XXX range (aka "PowerPC G4")
ca:PowerPC

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