VHSIC Hardware Description Language

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VHDL or VHSIC Hardware Description Language, is commonly used as a design-entry language for field-programmable gate arrays and application-specific integrated circuits in electronic design automation of digital circuits.

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History

VHDL was originally developed at the behest of the US Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details.

The idea of being able to simulate these "documents" was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them according to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest cost, highest power efficiency, highest speed, or other requirements.

VHDL has a syntax that is essentially a subset of the Ada programming language, along with an added set of constructs to handle the parallelism inherent in hardware designs. VHDL is strongly-typed and case insensitive.

The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string.

A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value std_logic.

The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc.

More recently, the language has been extended by introducing signed and unsigned types to facilitate arithmetical operations, analog and mixed-signal circuit design extensions, VITAL (VHDL Initiative Towards ASIC Libraries), and microwave circuit design extensions.

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Discussion

VHDL a fairly general-purpose programming language, although it requires a simulator on which to run the code. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a testbench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. This is similar to the capabilities of the Verilog language. VHDL is a strongly typed language, and as a result is considered by some to be superior to Verilog. In fact there has always been quite an intense debate which amounts to a holy war amongst developers over which is the superior language. However, both languages make it easy for the unwary and inexperienced to produce code that simulates successfully, but that cannot be synthesized into a real device, or else is too large to be practicable. A particular pitfall in both languages is the accidental production of transparent latches rather than D-type flip-flops as storage elements.

The key advantage of VHDL when used for systems design is that it allows the behaviour of the required system to be described (modelled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behaviour, working together at the same time). This is unlike many of the other computing languages such as BASIC, Pascal, C, or lower-level assembly language which runs at machine code level, which all run sequentially, one instruction at a time on von Neumann architectures.

A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is actual hardware that is being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.

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Code examples

These are written in VHDL-93 with its more consistent syntax.

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D-type flip-flop

The following example is a D-type flip-flop with a synchronous reset that stores one bit of memory : 

--  VHDL example programme: DFlipFlop.vhd
  library IEEE;
  use IEEE.std_logic_1164.all;
  entity DFlipFlop is
     port (
        CLK : in STD_LOGIC;
        RST : in STD_LOGIC;
          D : in STD_LOGIC;
          Q : out STD_LOGIC
     );
  end DFlipFlop;

  architecture behaviour of DFlipFlop is
  begin
      
      process(CLK)
      begin
         if rising_edge(CLK) then
              if RST = '1' then
                 Q <= '0';
              else
                 Q <= D;
              end if;
         end if;             
      end process;

  end behaviour;
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Fibonacci series

The following example is a little more real-world: 

--  Fib.vhd
--
--  Fibonacci number sequence generator

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Fibonacci is
port
(
    Reset       : in    std_logic;
    Clock       : in    std_logic;
    Number      : out   unsigned(31 downto 0)
);
end Fibonacci;

architecture Rcingham of Fibonacci is

    signal  Previous    : natural;
    signal  Current     : natural;
    signal  Next_Fib    : natural;

begin

    Adder:
    Next_Fib <= Current + Previous;

    Registers:
    process (Clock, Reset) is
    begin
        if Reset = '1' then
            Previous <= 1;
            Current  <= 1;
        elsif rising_edge(Clock) then
            Previous <= Current;
            Current  <= Next_Fib;
        end if;
    end process Registers;

    Number <= to_unsigned(Previous, 32);

end Rcingham;

When simulated, it generates the Fibonacci sequence successfully, until Next_Fib overflows the range of the natural type.

When synthesized with an FPGA vendor's tools, an "Adder" module was implemented, as hoped for. Otherwise, the assignment statement would have to be replaced by a component instantiation to logic that implements that function.

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See also

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External links

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Tutorials, FAQs and guides

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Interested bodies

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Examples

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Software

  • GHDL, a complete FreeSoftware VHDL simulator, using the GCC technology
  • Signs, a free (BSD licensed) netlist synthesis and simulation tool that supports a subset of VHDL93
  • ASIMUT, a free/open-source VHDL simulator, included in ALLIANCE. ALLIANCE is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools.
  • Wave VCD Viewer. A VHDL simulation can produce VCD (Value Change Dump) file that saves simulation results. Wave VCD Viewer allows the designer to view the simulation results as waveforms in the windows environment.
  • VHDL Mode, an Emacs major mode for editing VHDL codeda:VHDL

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