Efficeon
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The Transmeta Efficeon processor is their second-generation 256-bit VLIW design which employs a software engine to convert code written for x86 processors to the native instruction set of the chip. Like its predecessor, the Transmeta Crusoe (a 128-bit VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint.
Efficeon most closely mirrors the feature set of Intel Pentium 4 processors, although, like AMD Opteron processors, it supports a fully integrated memory controller, a HyperTransport IO bus, and the NX bit, or no-execute, AMD64 x86 extension.
Efficeon's computational performance relative to mobile CPUs like the Intel Pentium M is thought to be lower, although little appears to be published about the relative performance of these competing processors.
Efficeon comes in two package types: a 783 and a 592 ball grid array. Its power consumation is moderate (5 watts at 1 GHz and 13 watts at 1.3 GHz), so it can be passively cooled.
Internally, the Efficeon has 2 ALU units, 2 load/store/add units, 2 execute units, 2 floating-point/MMX/SSE/SSE2 units, one branch prediction unit, one alias unit, and one control unit. This VLIW Processor can execute a 256-VLIW word per cycle, which is called a molecule and therefore has room and capability to execute 8 32-bit commands (called atoms) per cycle.
The Efficeon has 128k + 64k level 1 cache and a 1Mb or 0.5Mb level 2 cache on the chip. Additionally it has a translation cache for the dynamically translated x86 instructions by the code-morphing software.