Instruction set

From Free net encyclopedia

An instruction set, or instruction set architecture (ISA, but not to be confused with the ISA motherboard bus), describes the aspects of a computer architecture visible to a programmer, including the native datatypes, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O (if any).

An ISA includes a specification of the set of all binary codes (opcodes) that are the native form of commands implemented by a particular CPU design. The set of opcodes for a particular ISA is also known as the machine language for the ISA.

"Instruction set architecture" is sometimes used to distinguish this set of characteristics from the microarchitecture, which is the set of processor design techniques used to implement the instruction set (including microcode, pipelining, cache systems, and so forth). Computers with different microarchitectures can share a common instruction set. For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but have radically different internal designs.

This concept can be extended to unique ISAs like TIMI (Technology-Independent Machine Interface) present in the IBM System/38 and IBM AS/400. TIMI is an ISA that is implemented as low-level software and functionally resembles what is now referred to as a virtual machine. It was designed to increase the longevity of the platform and applications written for it, allowing the entire platform to be moved to very different hardware without having to modify any software except that which comprises TIMI itself. This allowed IBM to move the AS/400 platform from an older CISC architecture to the newer POWER architecture without having to rewrite any parts of the OS or software associated with it.

Contents

[edit]

Instruction set design

When designing microarchitectures, engineers use Register Transfer Language (RTL) to define the operation of each instruction of an ISA. Historically there have been 4 ways to store that description inside the CPU:

  • all early computer designers, and some of the simpler later RISC computer designers, hard-wired the instruction set.
  • Many CPU designers compiled the instruction set to a microcode ROM inside the CPU. (such as the Western Digital MCP-1600)
  • Some CPU designers compiled the instruction set to a writable RAM or FLASH inside the CPU (such as the Rekursiv processor and the Imsys Cjip)[1], or a FPGA (reconfigurable computing).

An ISA can also be emulated in software by a interpreter. Due to the additional translation needed for the emulation, this is usually slower than directly running programs on the hardware implementing that ISA. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready.

Some instruction set designers choose the "0xff" all-ones instruction (and the "00" all-zeros instruction) to be some kind of software interrupt [2].

Fast virtual machines are much easier to implement if an instruction set meets the Popek and Goldberg virtualization requirements.

On systems with multiple processors, non-blocking synchronization algorithms are much easier to implement if the instruction set includes support for something like "fetch-and-increment" or "load linked/store conditional (LL/SC)" or "atomic compare and swap".

[edit]

code density

In early computers, memory was expensive. The "code density" was an important characteristic of an instruction set. Many instruction sets have been specifically designed to have high code density.

One way of categorizing instruction sets is to count the maximum number of operands of any instruction in the set:

Fewer operands leads to fewer bits per instruction to select the operands, leading to better instruction set density ("code density").

Some RISC CPUs have 32 registers and a 3-operand instruction set, with some instructions involving 2 source registers and a destination register. This requires 15 bits in each instruction just to select the registers, which is part of the reason that many RISC processors use 32 bits per instruction.

RISC CPUs generally have lower code density than CISC CPUs. When RISC CPUs were first introduced, this was seen as a potentially fatal flaw.

Trying to achieve executable compression has lead to the idea of Kolmogorov complexity.

[edit]

List of ISAs

This list is far from comprehensive as old architectures are abandoned and new ones invented on a continual basis. There are many commercially available microprocessors and microcontrollers implementing ISAs in all shapes and sizes. Customised ISAs are also quite common in some applications, e.g. ARC International, application-specific integrated circuit, FPGA, and reconfigurable computing. Also see history of computing hardware.

[edit]

ISAs commonly implemented in hardware

[edit]

ISAs commonly implemented in software with hardware incarnations

[edit]

ISAs never implemented in hardware

[edit]

See also

[edit]

Categories of ISA

[edit]

Examples of commercially available ISA

[edit]

Others

[edit]

External links

es:Conjunto de instrucciones fr:Jeu d'instructions it:Instruction set he:סט פקודות hu:Utasításkészlet ja:命令セット pl:ISA (procesory) ru:Система команд tr:Komut kümesi uk:Архітектура системи команд

Retrieved from "http://www.netipedia.com/index.php/Instruction_set"